AVSBUS Slave IIP

AVSBUS Slave interface provides full support for the two-wire/ three-wire AVSBUS Slave synchronous serial interface, compatible with version 1.3.1 Part III of PMBus Bus Specification. Through its AVSBUS Slave compatibility, it provides a simple interface to a wide range of low-cost devices. AVSBUS Slave IIP is proven in FPGA environment. The host interface of the AVSBUS Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

AVSBUS Slave IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with AVSBus specification as defined in version 1.3.1 Part III of PMBus Bus Specification
  • Full AVSBus Slave Functionality
  • Supports 3-wire ,2-wire AVSBus interface
  • Supports Multiple back to back frames and status for higher bus efficiency upto 256 Commands and responses
  • Supports all AVSBus Commands as per specification
  • Supports all AVSBus Data types as per specification
  • Support Slave status response frames
  • Supports Slave pin zero interrupt
  • Supports Clock Resynchronization
  • Support Bus timeout function
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The AVSBUS Slave interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.