JESD207 BBIC IIP

JESD207 BBIC is full-featured, easy-to-use, synthesizable design, compatible with JESD207 Compliant. Through its JESD207 BBIC compatibility,it provides a simple interface to a wide range of low-cost devices. JESD204 BBIC IIP is proven in FPGA environment. The host interface of the JESD207 BBIC can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

JESD207 BBIC IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with JESD207 specification.
  • Full JESD207 BBIC functionality.
  • Supports half duplex data transfer.
  • Supports DDR source synchronous data transfer timing.
  • Supports both data path transactions and control plane transactions.
  • Supports data path transaction.
    • Supports transmit burst and receive burst.
    • Supports 12, 14 and 16 bits parallel data width.
    • Supports 2 way interleave and 4 way interleave transactions.
    • Supports 1T1R, 1T2R, 2T2R systems.
  • Supports to transmit and receive multiple parallel sample streams in data path interface
  • Supports control plane transaction.
    • Supports 4 wires write and 4 wires read.
    • Supports 3 wires write and 3 wires read.
    • 1bit command plus 7bit address control field format.
    • Serial clock can be stopped between transactions, reducing control plane power consumption to negligible levels.
    • Extended data transactions.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The JESD207 BBIC interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.