MIPI SOUNDWIRE MASTER IIP

MIPI SoundWire interface provides full support for the two-wire MIPI SoundWire Master synchronous serial interface, compatible with version 1.1x MIPI SoundWire Bus specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI SoundWire Master IP is proven in FPGA environment.The host interface of the MIPI SoundWire Master can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI SOUNDWIRE MASTER IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with MIPI SOUNDWIRE version 1.1x Specification.
  • Full MIPI SOUNDWIRE Master functionality
  • Host can supports upto 11 slaves.
  • Supports upto 8 data lanes.
  • Supports modified-NRZI data encoding.
  • Special internal register for each devices.
  • Supports configurable data width of 8,16 and 32.
  • Supports configurable PDI count, type, command FIFO depth, data lane count, data port memories.
  • Supports clearly de-marked clock domains.
  • Supports extensive clock gating.
  • Provides bi-directional DATA line and unidirectional CLK line.
  • Enumeration for device is supported.
  • Provides Arbitration mechanism to access the port.
  • Provides limited retransmission of Messages.
  • Supports Frame layer to interleave Control space and data space in a Sub frame.
  • Supports all Core Message types.
  • User Defined protocol is supported.
  • Supports Flow control mechanism.
  • Supports Collision Detection for Message channel as well as for Data channel.
  • Supports various Error Management mechanisms.
  • -Error on Segments.
  • -Framing error.
  • -Parity error.
  • -Messaging error.
  • -Error on Synchronization.
  • -CRC error.
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The MIPI SOUNDWIRE MASTER interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.