UART CONTROLLER IIP

UART CONTROLLER interface provides full support for the two-wire UART CONTROLLER synchronous serial interface, compatible with UART specification. Through its UART CONTROLLER compatibility, it provides a simple interface to a wide range of low-cost devices. UART CONTROLLER IIP is proven in FPGA environment.The host interface of the UART CONTROLLER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

UART CONTROLLER IIP IIP is supported natively in Verilog and VHDL

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  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Compliant with Standard UART 16550 Specification
  • Full UART Functionality
  • Transmit and receive commands allow the user to transmit and receive UART data
  • Supports Character Mode, FIFO Mode and Extended FIFO Mode
  • Supports 6, 7 and 8 data bits on serial inputs and output with 1,1.5 or 2 stop bits
  • Parity, Framing and Overflow error detection
  • Programmable Baud rate from 110 bps to 115.2 kbps
  • Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO
  • Full duplex operation
  • Fully configurable serial interface
  • Supports character width from 1 bit to 32 bits
  • Configurable receive FIFO depth
  • Programmable Word length, Stop bits and Parity
  • Automatic Data Formatting and status generation
  • Interrupt Controller
  • Modem Control interface with CTS,RTS,DSR,DTR,RI and DCD signals
  • Provides bidirectional IRDA 1.4 Interface
  • Programmable hardware flow control
  • GPIO are supported using read and write commands
  • Line break detection and generation
  • On-the-fly protocol and data checking
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The UART Controller interface is available in Source and netlist products.
    • The Source product is delivered in plain text verilog or VHDL or SystemC source code
    • Integration testbench and tests
    • Scripts for simulation and synthesis with support for common EDA tools
    • Documentation contains User's Guide and Release notes.