AHB2APB BRIDGE IIP

AHB2APB Bridge IP core is compliant with AMBA AHB and AMBA APB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.AHB2APB Bridge IIP is proven in FPGA environment.

AHB2APB BRIDGE IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with AMBA AHB specification
  • Compliant with AMBA APB3 , AMBA APB4 specification
  • Translates AHB transactions into APB transactions
  • Endianness and data widths of both the interfaces are configurable
  • Data Phase timeout to send error response when there are no responses from APB
  • Accepts pipelining transfer of AHB
  • Supports single and fixed size incrementing bursts
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The AHB2APB Bridge is available in Source and netlist products.
    • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.