CAN Controller IIP

CAN CONTROLLER interface provides full support for the two-wire CAN CONTROLLER synchronous serial interface, compatible with CAN 2.0 A/B ISO 11898 and CAN FD 1.1 specification. It supports the original Bosch protocol and ISO specifications as defined in ISO 1989, including time-triggered operation (TTCAN) as specified in ISO 19898-4 and is also optimized to support the popular AUTOSAR and SAE J1939 specifications. The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features. Through its CAN CONTROLLER compatibility, it provides a simple interface to a wide range of low-cost devices. CAN CONTROLLER IIP is proven in FPGA environment.The host interface of the CAN CONTROLLER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

CAN Controller IIP IIP is supported natively in Verilog and VHDL

Note: Only mails from offical mail ID will be processed

Request Datasheet Request Evaluation
  • Compliant with CAN 2.0 A/B ISO11898
  • Compliant with CAN FD 1.1
  • Optimized for SAE J1939 and AutoSAR
  • Full CAN transmit and receive functionality
  • Supports bit rate up to 1 Mbps
  • Supports all types of frames
    • Data frame
    • Remote frame
    • Error frame
    • Overload frame
  • Supports 11 bit Identifier as well as 29 bit Identifier
  • Supports Automatic response for Remote frame
  • Supports all types of error detection
    • Bit error
    • Stuff error
    • CRC error
    • Form error
    • Acknowledgement error
  • Supports Interrupt for each CAN bus error and arbitration lost with detailed bit position
  • Supports Programmable clock output
  • Supports Self reception of own messages
  • Supports Single shot transmission
  • Supports message acceptance using single filter and double filter
  • Supports TEC/REC error counter with read/write access
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
  • Functional safety features (B: No certification, with safety features, in line with the development process)
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The CAN Controller interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.