IEEE 1149.7 COMPACT TAP IIP

IEEE 1149.7 COMPACT TAP is full-featured, easy-to-use, synthesizable design, compatible with IEEE 1149.7 Compliant. Through its IEEE 1149.7 COMPACT TAP compatibility,it provides a simple interface to a wide range of low-cost devices. IEEE 1149.7 COMPACT TAP IIP is proven in FPGA environment.The host interface of the IEEE 1149.7 COMPACT TAP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

IEEE 1149.7 COMPACT TAP IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with IEEE 1149.7 standard specification.
  • Supports TAP.7 capability classes T0 to T5.
  • Supports Reset and Selection Unit (RSU) for class T0 optional features.
  • Supports Extended Protocol Unit (EPU) for classes T0 to T3.
  • Supports all mandatory and optional EPU commands.
  • Supports Advanced Protocol Unit (APU) for classes T4 and T5.
  • Supports Transport function with 1 or 2 physical data channels (PDC) each supporting up to 16 data channel clients (DCC).
  • Supports 4 and 2 pin interface as specified in IEEE 1149.7 CJTAG.
  • Supports all mandatory and optional scan formats (JScan, MScan, OScan, and SScan).
  • IEEE 1149.7 Compact TAP supports following scan terminology
    • Data Register Scan.
    • Instruction Register Scan.
    • Control Register Scan.
    • Zero-Bit Scan.
  • IEEE 1149.7 Compact TAP supports following scan topology
    • Series scan topology : Class T0 - T5
    • Star-4 scan topology : Class T3 - T5
    • Star-2 scan topology : Class T4 - T5
  • Can be extended with user defines instructions and registers.
  • Fully synthesizable.
  • Static synchronous design.
  • No internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The IEEE 1149.7 COMPACT TAP interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.