DFI LPDDR5 PHY IIP

DFI LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5 specification and DFI-version 5.0 Compliant. Through its DFI LPDDR5 compatibility,it provides a simple interface to a wide range of low-cost devices. DFI LPDDR5 IIP is proven in FPGA environment.The host interface of the DFI LPDDR5 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

DFI LPDDR5 PHY IIP IIP is supported natively in Verilog and VHDL

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  • Complaint with LPDDR5 protocol standard JESD209-5 Specification
  • Compliant with DFI version 5.0 Specification
  • Supports all speed grades as per specification
  • Supports 2:1 and 4:1 Clock Ratio Mode
  • Support 16 and 32 bit data path widths, supporting single x32 channel or two x16 channels.
  • Support for byte-mode DRAM devices.
  • Support for write/read preamble/postamble settings.
  • Supports low power mode
  • Supports following training modes.
    • ZQ Calibration
    • Command bus training
    • CA/DQ Vref training
    • WCK2CK leveling
    • Duty cycle adjuster
    • Duty cycle monitor
    • Read DQ calibration
    • WCK-DQ training
    • RDQS toggle mode
    • Enhanced RDQS training mode
    • Read-Write based WCK-RDQS_t training mode
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The DFI LPDDR5 interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.