DMA Controller with TileLink IIP

DMA Controller with TileLink interface is full featured, easy-to-use, synthesizable design that can be used with TileLink based systems as a controller to transfer data directly from system memory to IP core or from IP core to system memory. Through its compatibility, it provides a simple interface to any IP core with the appropriate logic in between.

DMA Controller with TileLink IIP IIP is supported natively in Verilog and VHDL

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  • Supports Single channel DMA Transmit and DMA Receive Engine
  • Supports access for Ring and Chained Descriptor Structures
  • Configurable Transmit and Receive Engine based on Host Memory Data Width
  • Configurable support by DMA Transmit and Receive Engine for both of the endianness of the host memory (Little / Big Endian)
  • Supports configurable DMA Transmit and DMA Receive FIFO based on Host Memory Data width
  • Supports hardware DMA Control registers that can be written and read by CPU
  • Round Robin algorithm for arbitration between DMA Transmit and Receive Engine to access TileLink Bus
  • Uses TileLink Interface to get Receive and Transmit descriptors and transfer the data to/from the system memory from/to FIFO inside the DMA controller
  • User logic to map data fetched from Host to IP core or from IP core to host
  • Compliant with TileLink specification v1.7.1
  • Generate full 32-bit addresses on the TileLink interface
  • Supports 8/16/32/64-bit wide data transfers
  • Supports both single data and burst data transfers, with burst size based on the burst length field in the DMA control registers
  • DMA supports full duplex operation, processing read and write transfers at the same time
  • Interrupts CPU on completion of a DMA transfer or an error
  • Fully synthesizable
  • Static synchronous design
    • Single Site license option is provided to companies designing in a single site
    • Multi Sites license option is provided to companies designing in multiple sites
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs
    • The DMA Controller with TileLink interface is available in Source and netlist products
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes