eDP RECEIVER IIP

eDP Receiver core is compliant with standard eDP 1.4b specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. eDP Receiver IIP is proven in FPGA environment. The Receiver interface of the eDP can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

eDP RECEIVER IIP IIP is supported natively in Verilog and VHDL

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  • Supports eDP 1.4b specification
  • Supports full eDP Receiver functionality
  • Supports multi lanes upto 4 lanes.
  • Supports main link, Aux link and Hot plug functionality.
  • Supports packing of all the video formats supported by the display port
  • Supports HPD based link training.
  • Supports deskew in sink device mode
  • Supports scrambler as in Display port specification
  • Supports scrambler reset after every 512th symbols.
  • Supports RGB, YCBCR444, YCBCR422, YCBCR420, Y-Only and RAW color format.
  • Supports PSR (Panel Self Refresh) entry and exit.
  • Supports frame number identification in PSR.
  • Supports Selective update (partial frame update) during Panel Self Refresh (PSR)
  • Supports PSR2(Panel Self Refresh) as per spec eDPv1.4b
  • Supports Multi SST operation(MSO)
    • Two SST Links with one Lane each (two Lanes total), 2x1
    • Two SST Links with two Lanes each (four Lanes total), 2x2
    • Four SST Links with one Lane each (four Lanes total), 4x1
  • Supports Advanced Link Power Management to reduce wake latency
  • Supports GTC-based video timing synchronization
  • Supports Display stream compression as per spec eDPv1.4b
  • Supports PSR Secondary Data Packet.
  • Supports Display Backlight Control Using DPCD Registers.
  • Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces
  • Supports high-bandwidth Digital Content Protection System version1.3 (HDCP v1.3)
  • Supports high-bandwidth Digital Content Protection System version2.2 (HDCP v2.2)
    • Supports for HDCP2.2 with full authentication
    • Supports for HDCP2.2 with bypass the authentication
  • Supports high-bandwidth Digital Content Protection System version2.3 (HDCP v2.3)
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The eDP Receiver interface is available in Source and netlist products.
    • The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.