FEC RS (254,250) IIP

FEC RS (254,250) core is compliant with standard VESA Display Port version 1.4/2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (254,250) IIP is proven in FPGA environment. The host interface of the FEC RS (254,250) can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

FEC RS (254,250) IIP IIP is supported natively in Verilog and VHDL

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  • VESA Display Port version 1.4/2.0 compliant.
  • Supports full FEC functionality.
  • Supports Reed Solomon (254,250) FEC, 8-bit symbols.
  • Supports the parity generation of 32 bits.
  • Supports the bit locker mechanism.
  • Supports the Syndrome calculation.
  • Supports the Berlekamp's algorithm.
  • Supports the Chien search for error position.
  • Supports the Error correction.
  • Supports up to the 8 bits of error correction in sample.
  • Supports the pipelined mechanism for the error correction.
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The FEC RS (254,250) interface is available in Source and netlist products.
    • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.