FEC RS (528,514) core is compliant with standard CPRI 7.0 Specification and IEEE Standard 802.3.2018 Ethernet specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (528,514) IIP is proven in FPGA environment. The host interface of the FEC RS (528,514) can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
FEC RS (528,514) IIP IIP is supported natively in Verilog and VHDL
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