GPIO IIP

GPIO provides general purpose input output interface with AXI, AHB, Avalon and APB, compatible with standard protocol of GPIO specifications. Through its GPIO compatibility, it provides a simple interface to a wide range of low-cost devices. GPIO IIP is proven in FPGA environment. The host interface of the GPIO can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

GPIO IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with standard protocol of GPIO specification
  • Supports single channel
  • Supports configurable channel width for GPIO pins from 1 to 32 bits
  • Supports dynamic programming of each GPIO bit as input or output
  • Supports dynamic programming of each GPIO drive strength
  • Supports dynamic programming of each GPIO to enable/disable pullup/pulldown
  • Supports dynamic programming of each GPIO to control trigger as level or edge
  • Supports dynamic programming of each GPIO to control trigger as active low or active high level trigger
  • Supports dynamic programming of each GPIO to control trigger as falling edge or rising edge trigger
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The GPIO interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.