HBM2E Controller IIP

HBM2E is full-featured, easy-to-use, synthesizable design, compatible with HBM2E JESD235B and JESD235C with revision 4.10 specification and DFI-version 4.0 or 5.0 specification Compliant. Through its HBM2E compatibility, it provides a simple interface to a wide range of low-cost devices. HBM2E IIP is proven in FPGA environment.The host interface of the HBM2E can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

HBM2E Controller IIP IIP is supported natively in Verilog and VHDL

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  • Supports HBM2E protocol standard JESD235B and JESD235C with revision 4.10 Specification.
  • Compliant with DFI version 4.0 or 5.0 Specification.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  • Supports controllable outstanding transactions for AXI write and read channels.
  • Supports in port arbitration and multi port arbitration.
  • Supports user programmable page policy.
    • Closed page policy
    • Open page policy
  • Supports Error Checking and correction (ECC).
  • Supports retry on ECC error, with retry limit user controllable.
  • Supports high clock speeds in ASIC and FPGA.
  • Supports low latency for write and read path.
  • Supports reordering of transactions for higher performance.
  • Supports all the HBM2E commands as per the specs.
  • Supports burst length of 2 and 4.
  • Supports all Interface Groups.
  • Supports programmable Read/Write latency timings.
  • Supports bank grouping.
  • Supports DRAM Clock disabling feature.
  • Supports Low power control features.
  • Supports Data bit enable/disable feature.
  • Supports 8, 16, 32 and 64 banks per channel.
  • Supports 1:2 MC to PHY frequency ratio.
  • Supports up to 8 channels per stack.
  • Supports Extended Addressing.
  • Supports Extended Write latency and read latency.
  • Supports all mode registers programming.
  • Supports Data Bus Inversion (DBI) for write and read.
  • Supports legacy mode and pseudo channel mode operation (64 DQ width for pseudo channel mode).
  • Supports self-refresh modes.
  • Supports channel density of 1GB to 128 GB.
  • Supports 128 DQ width + optional ECC pin support/channel.
  • Supports ECC.
  • Supports Error signaling.
  • Supports DFI Read/Write Chip Select.
  • Supports write data mask and data strobe features.
  • Supports for power down features.
  • Supports for input clock stop and frequency change.
  • Supports for target row refresh mode.
  • Supports for temperature compensated refresh reporting.
  • Supports for IEEE standard 1500.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The HBM2E interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.