I2C Slave IIP

I2C Slave interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 6.0 specification. Through its I2C compatibility, it provides a simple interface to a wide range of low-cost devices. I2C Slave IIP is proven in FPGA environment.The host interface of the I2C can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

I2C Slave IIP IIP is supported natively in Verilog and VHDL

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Compliant with I2C version 6.0 specification
Full I2C Slave Functionality
Supports Start, Repeated start and Stop for all possible transfers
Supports 7bit/10bit Addressing
Supports following speed modes

Standard mode
Fast mode
Fast plus mode
High speed mode

Supports General call address handling

Supports for clock stretching

Fully synthesizable

Static synchronous design

Positive edge clocking and no internal tri-states

Scan test ready

Simple interface allows easy connection to microprocessor/microcontroller devices

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

The I2C Slave interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.