I2S Controller IIP

I2S Controller interface provides full support for the two-wire I2S synchronous serial interface, compatible with I2S specification. Through its I2S compatibility, it provides a simple interface to a wide range of low-cost devices. I2S Controller IIP is proven in FPGA environment. The host interface of I2S can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

I2S Controller IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with the Philips I2S Bus Specification
  • Master mode as Controller
  • Slave mode as transmitter and receiver
  • Bidirectional operation through two unidirectional serial data lines
  • Simultaneous audio playback and recording
  • Supports configurable 8/16/24/32 bit DAC/ADC resolution
  • Supports 44.1KHz audio sampling frequencies
  • Supports multiple audio data formats
  • I2S format
  • Left Justified
  • Right Justified
  • Programmable word select resolution (8-32 clock cycles) in master mode
  • Four reference clock sources selectable for bit clock generation with programmable clock divider
  • Interrupt-driven or DMA operation
  • Four 8-word FIFOs (left/right; transmit/receive)
  • Programmable FIFO threshold levels for interrupt or DMA request generation
  • Additional interrupts for transmit FIFO under run and receive FIFO over run with separate enables
  • Freeze/suspend operation for system debug support
  • Local clock gating for minimal power consumption
  • Fully Synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices.
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The I2S Controller interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.