INTERLAKEN IIP

Interlaken interface provides full support for the Interlaken synchronous serial interface, compatible with Interlaken version 1.2 specification. Through its Interlaken compatibility, it provides a simple interface to a wide range of low-cost devices. Interlaken IIP is proven in FPGA environment. The host interface of the Interlaken can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

INTERLAKEN IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with Interlaken protocol specification v1.2
  • Interlaken look as side protocol 1.1
  • Interlaken retransmission extension specification 1.2
  • Interlaken Reed-Solomon Forward Error Correction Extension 1.1
  • Interlaken Interoperability Recommendations 1.11
  • Interlaken Dual Calendar Extension 1.0
  • Supports up to 1000Gbps
  • Supports single channel and multichannel (up to 4 channel)
  • Supports for 256 communications channels, or up to 64K with channel extension
  • Supports configurable number of lanes from 1 to 64 lanes
  • Supports configurable burst max, burst short and meta-frame length.
  • Supports the In-bound/out-bound flow control
  • Supports burst interleaved and Packet mode
  • Supports 80,64,40,32, 20,16,10 and 8 bit per lane serdes interface
  • Supports 64/67 encoding and decoding with DC balance
  • Supports automatic word and lane alignment
  • Supports self-synchronizing data scrambler
  • Supports status messaging
  • Supports ILA overhead insertion and extraction
  • Supports CRC32 generation and checking for lane data integrity
  • Supports transmit and receive clock and data rate decoupling with programmable asynchronous FIFO
  • Supports unidirectional and bidirectional operation
  • Supports lane protection
  • Supports test pattern generation and checker
  • A simple control word structure to delineate packets, similar in function to SPI4.2
  • Optional support for scheduling enhancement to avoid unused bandwidth by using decision algorithm
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The Interlaken interface is available in Source and netlist products.
    • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.