LPDDR4 Controller IIP

LPDDR4 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR4 JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4X and JESD209-4Y (Proposed) specification and DFI-version 4.0 or 5.0 specification Compliant. Through its LPDDR4 compatibility, it provides a simple interface to a wide range of low-cost devices. LPDDR4 IIP is proven in FPGA environment.The host interface of the LPDDR4 can be simpleinterface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

LPDDR4 Controller IIP IIP is supported natively in Verilog and VHDL

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  • Supports LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4X and JESD209-4Y (Proposed) Specification.
  • Compliant with DFI version 4.0 or 5.0 Specification.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  • Supports controllable outstanding transactions for AXI write and read channels
  • Supports in port arbitration and multi port arbitration.
  • Supports user programmable page policy.
    • Closed page policy
    • Open page policy
  • Supports Error Checking and correction (ECC).
  • Supports retry on ECC error, with retry limit user controllable.
  • Supports high clock speeds in ASIC and FPGA.
  • Supports low latency for write and read path.
  • Supports reordering of transactions for higher performance.
  • Supports up to 32 GB device density.
  • Supports the X8 and X16 device type.
  • Supports on-the-fly in burst lengths.
  • Supports Byte mode.
  • Supports Single-ended mode.
  • Supports Write leveling.
  • Supports CA training and DQ Vref training.
  • Supports all speed grades as per specification.
  • Supports Mode Registers programming.
  • Supports Sequential burst type.
  • Supports Programmable burst lengths of 16 and 32.
  • Supports Multiple Outstanding transaction.
  • Supports In-port Arbitration using QoS.
  • Supports Write Data Mask operation.
  • Supports Data Bus Inversion for Write and Read.
  • Supports CRC and ECC for Write and Read Operations.
  • Supports Self Refresh and Power Down operation.
  • Supports Precharge Command modes.
  • Supports 1:4 Controller to DFI PHY frequency ratio.
  • Supports Programmable clock frequency operation.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices.
  • Build in self test to test all locations in memory to identify damaged locations
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The LPDDR4 interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.