LPDDR5 Controller IIP

LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5, JESD209-5A and JESD209-5B specification and DFI-version 5.0 specification Compliant. Through its LPDDR5 compatibility,it provides a simple interface to a wide range of low-cost devices. LPDDR5 IIP is proven in FPGA environment.The host interface of the LPDDR5 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

LPDDR5 Controller IIP IIP is supported natively in Verilog and VHDL

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  • Supports LPDDR5 protocol standard JESD209-5, JESD209-5A and JESD209-5B Specification.
  • Compliant with DFI version 5.0 Specification.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  • Supports controllable outstanding transactions for AXI write and read channels
  • Supports in port arbitration and multi port arbitration.
  • Supports user programmable page policy.
    • Closed page policy
    • Open page policy
  • Supports Error Checking and correction (ECC).
  • Supports retry on ECC error, with retry limit user controllable.
  • Supports high clock speeds in ASIC and FPGA.
  • Supports low latency for write and read path.
  • Supports reordering of transactions for higher performance.
  • Supports up to 32GB device density.
  • Supports X8 and X16 devices.
  • Supports all speed grades as per specification.
  • Supports Mode registers programming.
  • Supports programmable write latency and read latency.
  • Supports programmable burst length of 16 and 32.
  • Supports BG, 8B and 16B bank organization modes.
  • Supports burst sequence.
  • Supports Optimized Refresh.
  • Supports Refresh Management Command.
  • Supports Read DBI and Write DBI operation.
  • Supports Multiple Outstanding transaction.
  • Supports In-port Arbitration using QoS.
  • Supports WCK2CK Sync operation.
  • Supports for WCK Control.
  • Supports 2:1 and 4:1 Clock Ratio Modes.
  • Supports CRC and ECC for Write and Read Operations.
  • Supports Command Address Parity features.
  • Supports Write data mask operation.
  • Supports Deep Sleep mode.
  • Supports for Self Refresh operation and Power Down mode.
  • Supports 1:4 Controller to DFI PHY frequency ratio.
  • Supports Programmable clock frequency operation.
  • Supports Frequency Set point operation.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices.
  • Build in self test to test all locations in memory to identify damaged locations
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The LPDDR5 interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases.
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
    • IP-XACT RDL generated address map.
    • Firmware code and Linux driver package.
    • Documentation contains User's Guide and Release notes.