MIPI CSI-2 Receiver interface provides full support for the two-wire MIPI CSI2 serial interface, compatible with MIPI CSI-2 Specification version 2.1. It is typically residing in an image application processor and provides communication to MIPI CSI-2 transmitter in a camera module over the serial PHY link. MIPI CSI-2 Receiver IIP is fully configurable and proven in FPGA environment. The host interface of the MIPI CSI-2 Receiver IP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
MIPI CSI-2 Receiver IIP IIP is supported natively in Verilog and VHDL
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