MIPI Debug Taget IP

MIPI Debug Target interface IP provides full support for the two-wire MIPI Debug Target synchronous serial interface, compatible with MIPI Debug Specification version 1.0. Through its MIPI Debug Target compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI Debug Target IP is proven in FPGA environment. The host interface of the MIPI Debug Target can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI Debug Taget IP IIP is supported natively in Verilog and VHDL

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  • Compliant with MIPI Debug version 1.0 specification.
  • Full MIPI MIPI Debug functionality.
  • Support full I3C Slave with Hot Join, IBI, DAA and HDR mode.
  • Full Link and Network/Transport layer.
  • Support Network adaptors for following
    • SPP
    • STP
    • SAM
    • TWP
    • UART
  • Supports upto 16 Network Adaptors.
  • Fully synthesizabl
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The MIPI Debug Target interface is available in Source and netlist products.
    • The Source product is delivered in plain text verilog or VHDL or SystemC source code
    • Integration testbench and tests
    • Scripts for simulation and synthesis with support for common EDA tools
    • Documentation contains User's Guide and Release notes.