MIPI I3C Slave IIP

MIPI I3C SLAVE interface provides full support for the two-wire MIPI I3C SLAVE synchronous serial interface, compatible with MIPI I3C specification version 2.0. Through its MIPI I3C SLAVE compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI I3C SLAVE IIP is proven in FPGA environment.The host interfaceof the MIPI I3C SLAVE can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI I3C Slave IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with MIPI I3C version 1.1 specification.
  • Full MIPI I3C Slave functionality.
  • Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported.
    • Standard speed
  • Supports the following topologies
    • Single Master-Multi Slave
    • Single Master-Single Slave
    • Multi Master-Multi slave
    • Multi Master-Single Slave
  • Legacy I2C device co-existence on the same bus
  • Supports Dynamic Address Assignment including Static Addressing for legacy I2C Devices
  • Supports I3C address arbitration
  • Supports Single Data Rate (SDR) messaging.
    • SDR with CCC Directed addressing
    • SDR with CCC Broadcasted addressing
  • Supports High Data Rate (HDR) messaging
    • HDR-Dual Data Rate Mode (HDR-DDR)
    • HDR-Ternary Symbol Legacy Mode (HDR-TSL)
    • HDR-Ternary Symbol Pure-Bus Mode (HDR-TSP)
  • In-Band Interrupt support
  • Hot-Join support
  • Secondary master request support
  • Dynamic Address Assignment support (DAA).
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The MIPI I3C SLAVE interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.