MIPI RFFE Master IIP

MIPI RFFE Master interface provides full support for the two-wire MIPI RFFE synchronous serial interface, compatible with RFFE specification. Through its RFFE compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI RFFE Master IIP is proven in FPGA environment. The host interface of the MIPI RFFE can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI RFFE Master IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with version 3.0 MIPI RFFE Specifications.
  • Full MIPI RFFE Master Functionality.
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
    • Bus ownership transfer
    • Interrupt polling
    • Master write and read
    • Master context write and context read
  • Supports extended register read/writes
  • Supports interrupt summary and identification command sequence
  • Supports Master ownership handover
  • Support Master write and read sequence
  • Support Trigger and Extended trigger modes
  • Support Masked write command sequence
  • Support Silent Master initiated bus park
  • Supports Bus Clocked Condition
  • Supports Timed Trigger
  • Supports Mappable Triggers
  • Support Synchronous read
  • Supports Low power testing
  • Bus-accurate timing
  • Supports half speed
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Optionally this core can be built to have SPI or I2C interface for application where slave can have multiple interfaces like RFFE or SPI or I2C Interface
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The MIPI RFFE Master interface is available in Source and netlist products.
    • The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and linux driver package
    • Documentation contains User's Guide and Release notes.