Quad SPI Master IIP

QUAD SPI MASTER is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of SPI Vendor Specifications.Through its QUAD SPI compatibility,it provides a simple interface to a wide range of low-cost devices. QUAD SPI MASTER IIP is proven in FPGA environment.The host interface of the QUAD SPI MASTER can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

Quad SPI Master IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with features of Vendors such as Macronix, Winbond, Cypress and Micron SPI Specifications.
  • Full QUAD SPI Master Functionality.
  • Supporting Operating Modes: Single I/O, Dual I/O and QUAD I/O with Single and Double Transfer Rate (STR and DTR).
  • Supports Frequency up to 166MHz
  • Supporting Resets: Software Reset using Reset Command and Hardware Reset using Reset Pin
  • Support 3-byte and 4-byte Addressing Capability to Enable Memory Access Beyond 128Mb
  • Configuration Capability:
    • Volatile and Non-Volatile Configuration register settings to change the mode of the model, dummy cycle numbers for FAST Read Operation and 3-byte and 4-byte Addressing
  • Supports a Wide Range of Device densities from 256Mb to 2Gb
  • Supports Preamble bit to inputted the Selected Preamble Pattern to the Dummy cycle
  • Configurable Transmit/Receive Data FIFO.
  • Direct Memory Access (DMA) support.
  • Supports of Fast Boot will have an ability to automatically execute read operation After Power on Reset or cycles without any Read command based on the Configuration of Fast Read Boot Register Values.
  • Supported Read Instructions:
    • READ
    • FAST READ
    • 2READ
    • DREAD
    • 4READ
    • QREAD
  • Supported Write Instructions:
    • Page Program
    • Dual Page Program and
    • Quad Page Program
  • Supports of Burst Length Command, user can to set 16-byte, 32-byte and 64-byte Wrap Bursts for Read Commands
  • Deep power down mode Support (Does not accept other commands except Release and Exit from the Deep Power Down Command)
  • Also supports Commands like Erase Commands, Security and Write Protection Commands with some other Additional Functionalities and Timing Commands
  • AHB Slave Interface for Register Programming and PIO data Transfer.
  • AHB Master Interface for DMA Transfer.
  • Fully synthesizable.
  • Static synchronous design.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The QUAD SPI MASTER interface is available in Source and netlist products
    • The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and linux driver package
    • Documentation contains User's Guide and Release notes