SDIO Host Controller IIP

SDIO HOST interface provides full support for the SDIO HOST CONTROLLER synchronous serial interface, compatible with SDIO version 4.10 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. SDIO HOST IIP is proven in FPGA environment. The host interface of the SDIO can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SDIO Host Controller IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with SD Host Controller Specification version 6.0
  • Compliant with SDIO Physical Specification version 6.10
  • Compliant with Part E1 SDIO specification 4.10
  • Supports SDMA, ADMA2 and ADMA3 modes
  • Supports all features of Part 1 eSD(Embedded SD) addendum version 2.10
  • Supports SD Memory, SD I/O card, Combo card
  • Supports 1-bit, 4-bit, 8-bit SD bus mode and SPI Bus mode
  • Supports all commands/response types
  • Supports SDR12, SDR25 ,DDR50, SDR 50 and SDR104 modes
  • Supports Single byte, Single block , Multi –block(finite and infinite) transfers
  • Supports command queue
  • Supports suspend and resume
  • Supports read wait
  • Supports card detection
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Optionally UHS - II support can be added
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The SDIO HOST IP Controller is available in Source and netlist products.
    • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.