SMBUS Master IIP

SMBUS Master interface provides full support for the two-wire SMBUS Master synchronous serial interface, compatible with SMBUS version 3.1 specification. Through its SMBUS Master compatibility, it provides a simple interface to a wide range of low-cost devices. SMBUS Master IIP is proven in FPGA environment. The host interface of the SMBUS Master can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SMBUS Master IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with SMBus version 3.1 specification
  • Supports HCI and Non HCI Interface
  • Full SMBus Master Functionality
  • Supports command code Protocols
    • Write Byte/Word
    • Read Byte/Word
    • Process Call
    • Block Write/Read
    • Block Write-Block Read Process Call
    • Write 32 Protocol
    • Read 32 Protocol
    • Write 64 Protocol
    • Read 64 Protocol
  • Supports Non command code Protocols
    • Quick Command Protocol
    • Send Byte Protocol
    • Receive Byte Protocol
  • Supports Address Resolution Protocol
  • Supports SMBAlert signal and SMBsus signal
  • Supports Packet Error Checking
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The SMBUS Master interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.