TileLink To AHB Bridge IIP

TileLink to AHB Bridge IP core is compliant with SiFive Tilelink and AMBA AHB Specification. Through its compatibility,it provides a simple interface to a wide range of low-cost devices. Tilelink2ahb Bridge IIP is proven in FPGA environment.

TileLink To AHB Bridge IIP IIP is supported natively in Verilog and VHDL

Note: Only mails from offical mail ID will be processed

Request Datasheet Request Evaluation
  • Compliant with SiFive TileLink specification version 1.8.1
  • Compliant with AMBA AHB specification
  • Translates Tilelink transactions into AHB transactions
  • Support for data phase timeout when AHB interface does not send response
  • Supports single and fixed size incrementing bursts
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single site license option is provided to companies designing in a single site.
    • Multi sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The TileLink to AHB Bridge is available in Source and netlist products.
    • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.