TS5 Slave IIP

TS5 Slave interface provides full support for the two-wire TS5 synchronous serial interface, compatible with JEDEC TS5111, TS5110 specifications. Through its TS5 compatibility, it provides a simple interface to a wide range of low-cost devices. TS5 Slave IIP is proven in FPGA environment.The host interface of the TS5 Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

TS5 Slave IIP IIP is supported natively in Verilog and VHDL

Note: Only mails from offical mail ID will be processed

Request Datasheet Request Evaluation
  • Compliant with JEDEC TS5111, TS5110 specifications.
  • Full TS5 Slave Controller functionality.
  • Supports two wire bus serial interface
  • Supports all the TS5 commands as per the specs
  • I2C with maximum speed up to 1 MHz
  • I3C with maximum speed up to 12.5 MHz
  • Supports two unique device addresses selected by SA pin.
  • Supports start, repeat start and stop for all possible transfers.
  • Supports START byte generation and handling.
  • Supports bus reset.
  • Supports in-band interrupts.
  • Supports parity error check.
  • Supports packet error check.
  • Supports device read address pointer mode.
  • Supports all error handling as per specs
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The TS5 Slave interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.