VIRTUAL GPIO IIP

Virtual GPIO interface provides host processor to peripheral connectivity using standard data interface such as PCIe, USB, UART, compatible with MIPI Virtual GPIO v0.9 standard. Through its Virtual GPIO compatibility, it provides a simple interface to a wide range of low-cost devices. Virtual GPIO IIP is proven in FPGA environment.The host interface of the Virtual GPIO can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

VIRTUAL GPIO IIP IIP is supported natively in Verilog and VHDL

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  • Compliant with standard protocol of MIPI Virtual GPIO v0.9 specification
  • Bi-directional Virtual GPIO state information exchange
  • Transmission latency within the permissible limits
  • Wide range of clock frequency support (from sleep clock to higher frequency (78 MHz)
  • Dynamically switchable clock gears
  • GPIO Stream Length programmability
  • Ability to detect physical interface failure under corner case conditions, such as power failure, or a watchdog timer bite that renders the SoC unable to communicate via standard bus-based communication.
  • Minimum to no software required for driving the interface For lower transmission latency, a third wire providing clock is permitted, making it a 3-Wire VGI interface
  • Minimum impact on power and die area
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
    • The Virtual GPIO interface is available in Source and netlist products.
    • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
    • Easy to use Verilog Test Environment with Verilog Testcases
    • Lint, CDC, Synthesis, Simulation Scripts with waiver files
    • IP-XACT RDL generated address map
    • Firmware code and Linux driver package
    • Documentation contains User's Guide and Release notes.