AC'97 CONTROLLER IIP

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AC'97 CONTROLLER interface provides full support for the AC'97 CONTROLLER synchronous serial interface, compatible with AC'97 2.2 specification. Through its AC'97 CONTROLLER compatibility, it provides a simple interface to a wide range of low-cost devices. AC'97 CONTROLLER IIP is proven in FPGA environment. The host interface of the AC'97 CONTROLLER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

AC'97 CONTROLLER IIP is supported natively in Verilog and VHDL

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  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports AC'97 2.2 specification
  • Supports AC'97 audio codec functionality
  • Supports variable and fixed sample rate support
  • Supports 16, 18 and 20 bit sample size support
  • Supports 6 output channel surround sound
  • Supports stereo input channel
  • Supports mono microphone channel
  • Supports external DMA engine
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's PCI MASTER SLAVE IP contains following

  • The AC'97 CONTROLLER interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.