RAPIDIO EP IIP

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RapidIO EP interface provides full support for the RapidIO EP synchronous serial interface, compatible with RapidIO Interconnect 2.2 specification. Through its RapidIO EP compatibility, it provides a simple interface to a wide range of low-cost devices. RapidIO EP IIP is proven in FPGA environment. The host interface of the RapidIO EP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

RAPIDIO EP IIP is supported natively in Verilog and VHDL

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  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports RapidIO Interconnect 2.2 specification
  • Supports all Capability Registers(CARs) and Configuration and Status Registers(CSRs)
  • Supports efficient receive and transmit buffering scheme
  • Supports 34-bit addressing
  • Supports 8-bit device ID
  • Supports programmable source ID on all outgoing packets
  • Supports request class transactions: NREAD and ATOMIC set/clr/inc/dec for read-modify-write operations
  • Supports all transaction flows
  • Supports write class transactions: NWRITE, NWRITE_R
  • Supports Doorbell and Data Message class transactions
  • Supports streaming write class transactions: SWRITE
  • Supports the below physical layer features
    • 1x/2x/4x serial lane support with integrated transceivers
    • Supports per-lane speeds of 1.25, 2.5, 3.125, 5.0 and 6.25Gbaud
    • Receive/Transmit packet buffering and error detection
    • Automatic freeing of resources used by acknowledged packets
    • Automatic retransmission of retried packets
  • Supports interrupt for each error detection and for complete serial message reception
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's MIL_STD_1553 IP contains following

  • The RapidIO EP interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.