ETHERNET IIP

Ethernet interface provides full support for the Ethernet synchronous serial interface, compatible with IEEE 802.3 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet IIP is proven in FPGA environment. The host interface of the Ethernet can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

ETHERNET IIP is supported natively in Verilog and VHDL

Note: Only mails from offical mail ID will be processed

Request Datasheet Request Evaluation
  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports Tri-mode Ethernet specification
  • Half duplex support for the 10_100mbps mode
  • Implements IEEE 802.3 Ethernet specification
  • Used for inferred RAMs and PADs to reduce the technology dependence
  • Supports pause frame generation and termination
  • Transmitting frames source MAC address insertion
  • Receiving frames destination MAC address filter
  • Receiving broadcast frames throughout constraint
  • Supports Jumbo frame 9.6K
  • MAC control and data frame support
  • Supports pause frame detection
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's Ethernet IP contains following

  • The Ethernet interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.

Note: Only mails from offical mail ID will be processed

Request Datasheet Request Evaluation