SMBUS SLAVE IIP

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SMBUS Slave interface provides full support for the two-wire SMBUS Slave synchronous serial interface, compatible with SMBUS version 2.0 specification. Through its SMBUS Slave compatibility, it provides a simple interface to a wide range of low-cost devices. SMBUS Slave IIP is proven in FPGA environment. The host interface of the SMBUS Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

SMBUS SLAVE IIP is supported natively in Verilog and VHDL

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  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports SMBUS version 2.0 specification
  • Full SMBUS Slave transmit and receive functionality
  • Supports start, repeat start and stop for all possible transfers
  • Supports bus-accurate timing
  • Supports clock synchronization
  • Supports ARP command generation and response
  • Supports Packet Error Checking
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's PCI MASTER SLAVE IP contains following

  • The SMBUS Slave interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.