SPI SLAVE IIP

  • Home
  • SPI SLAVE IIP

SPI Slave interface provides full support for the both three and four wire SPI synchronous serial interface, compatible with SPI specification SPI Block Guide V04.01. Through its SPI compatibility, it provides a simple interface to a wide range of low-cost devices. SPI Slave IIP is proven in ASIC.The host interface of the SPI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

SPI SLAVE IIP is supported natively in Verilog and VHDL

Note: Only mails from offical mail ID will be processed

Request Datasheet Request Evaluation
  • Supports SPI Block Guide V04.01 Specification
  • Full SPI Slave functionality
  • Supports following frames
    • Sleep Frame
    • Wakeup Frame
    • Write Frame
    • Read Frame
  • Supports 8 bit and 16 bit address
  • Support single and burst transfer mode
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Slave IP can be build to have additional slave interface blocks like I2C, in addition to SPI slave functionality.
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's CAN Controller IP contains following.

  • The CAN Controller interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.