MIPI BIF SLAVE IIP

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MIPI BIF Slave interface provides full support for the two-wire MIPI BIF synchronous serial interface, compatible with BIF specification. Through its BIF compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI BIF Slave IIP is proven in FPGA environment. The host interface of the MIPI BIF can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

MIPI BIF SLAVE IIP is supported natively in Verilog and VHDL

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  • Supports 1.0 MIPI BIF Specification
  • Full MIPI BIF Slave functionality
  • Supports following frames
    • reset
    • power control
    • Interrupt
    • Burst
    • Multicast
    • UID search
    • Device specific
  • Supports Low power modes
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's MIPI BIF Slave IP contains following.

  • The MIPI BIF Slave interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.