MIL_STD_1553 IIP

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MIL_STD_1553 interface provides full support for the MIL_STD_1553 synchronous serial interface, compatible with MIL_STD_1553B specification. Through its MIL_STD_1553 compatibility, it provides a simple interface to a wide range of low-cost devices. MIL_STD_1553 IIP is proven in FPGA environment. The host interface of the MIL_STD_1553 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

MIL_STD_1553 IIP is supported natively in Verilog and VHDL

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  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports and implements MIL_STD_1553B specification
  • Supports remote terminal and bus controller
  • Supports configurable length of word length, default 20 bits
  • Supports configurable length of data bits, default 16 bits
  • Supports configurable message length per transfer
  • Supports NRZ and Manchester encoding
  • Supports all types of error detection
  • Supports all the mode codes and broadcast packet transactions
  • Supports single or multi bus control
  • Supports up to 31 remote terminals
  • Fully synthesizable
  • Static synchronous design
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's MIL_STD_1553 IP contains following

  • The MIL_STD_1553 interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.