SAE J2716 Sensor interface provides full support for the SENT SAE J2716 synchronous serial interface, compatible with SENT specification SAE J2716 JAN2010. Through its SAE J2716 compatibility, it provides a simple interface to a wide range of low-cost devices. SAE J2716 Sensor IIP is proven in FPGA environment.

SAE J2716 SENSOR IIP is supported natively in Verilog and VHDL

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  • Supports SENT specification SAE J2716
  • Supports all types of frames
    • Short Serial Message Format
    • Enhanced Serial Message Format
  • Enhanced Serial Message Format supports two different configurations
    • 12-bit data and 8-bit message ID
    • 16-bit data and 4-bit message ID
  • Supports programmable clock frequency of operation
  • Supports programmable number of data nibbles
  • Supports programmable nibble pulse lengths
    • Minimum length - 12 clock ticks
    • Maximum length - 27 clock ticks
  • Supports pause pulse properties
    • Minimum length - 12 clock ticks
    • Maximum length - 768 clock ticks
  • Supports both 4-bit CRC and 6-bit CRC
  • Fully Synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to sensors.
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

SmartDV's SAE J2716 Sensor IP contains following.

  • The SAE J2716 Sensor interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.

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