I2C SLAVE IIP

  • Home
  • I2C SLAVE IIP

I2C Slave interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 2.1 specification. Through its I2C compatibility, it provides a simple interface to a wide range of low-cost devices. I2C Slave IIP is proven in FPGA environment.The host interface of the I2C can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

2C SLAVE IIP is supported natively in Verilog and VHDL

Note: Only mails from offical mail ID will be processed

Request Datasheet Request Evaluation
  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports I2C version 2.1 specification
  • Supports Start, repeat start and stop for all possible transfers
  • Supports 7b/10b Addressing
  • Supports following speed modes
    • Standard mode
    • Fast mode
    • High speed mode
  • Bus-accurate timing
  • Supports clock stretching
  • Supports General call address handling
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready/li>
  • Simple interface allows easy connection to microprocessor/micro-controller devices
  • All receive channels controled from one set of configuraion registers
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Note: Only mails from offical mail ID will be processed Request Datasheet Request Evaluation SmartDV's I2S Master IP contains following.

  • The I2S Slave interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog or VHDL or SystemC source code
  • Integration testbench and tests
  • Scripts for simulation and synthesis with support for common EDA tools
  • Documentation contains User's Guide and Release notes.