MIPI RFFE SPI SLAVE IIP

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MIPI RFFE SPI Slave interface provides full support for the two-wire MIPI RFFE synchronous serial interface with SPI overlay, compatible with RFFE and SPI specification. Through its RFFE compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI RFFE SPI Slave IIP is proven in multiple ASIC.The host interface of the MIPI RFFE/SPI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.

MIPI RFFE SPI SLAVE IIP is supported natively in Verilog and VHDL

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  • Supports 1.1 MIPI RFFE Specification
  • Supports SPI Block Guide V04.01 Specification
  • Full MIPI RFFE Slave functionality
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
  • Supports extended register read/writes
  • Supports device enumeration
  • Supports Low power modes
  • Supports half speed
  • Full SPI Slave functionality
  • Supports following frames for SP1
    • Sleep Frame
    • Wakeup Frame
    • Write Frame
    • Read Frame
  • Supports 8 bit and 16 bit address for SPI
  • Support single and burst transfer mode for SPI
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/micro-controller devices
  • Slave IP can be build to have additional slave interface blocks like SPI or I2C, in addition to RFFE slave functionality.
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

    SmartDV's MIPI RFFE SPI Slave IP contains following.

    • The MIPI RFFE SPI Slave interface is available in Source and netlist products.
    • The Source product is delivered in plain text verilog or VHDL or SystemC source code
    • Integration testbench and tests
    • Scripts for simulation and synthesis with support for common EDA tools
    • Documentation contains User's Guide and Release notes.