CAN CONTROLLER IIP

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CAN CONTROLLER interface provides full support for the two-wire CAN CONTROLLER synchronous serial interface, compatible with CAN 2.0 A/B ISO 11898 specification. Through its CAN CONTROLLER compatibility, it provides a simple interface to a wide range of low-cost devices. CAN CONTROLLER IIP is proven in FPGA environment.The host interface of the CAN CONTROLLER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol

CAN CONTROLLER IIP is supported natively in Verilog and VHDL

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  • Implemented in Unencrypted Verilog, VHDL and SystemC
  • Supports CAN 2.0 A/B ISO11898 compliant
  • Full CAN transmit and receive functionality
  • Supports bit rate up to 1 Mbps
  • Supports all types of frames
    • Data frame
    • Remote frame
    • Error frame
    • Overload frame
  • Supports 11 bit Identifier as well as 29 bit Identifier
  • Supports Automatic response for Remote frame
  • Supports all types of error detection
    • Bit error
    • Stuff error
    • CRC error
    • Form error
    • Acknowledgement error
  • Supports Interrupt for each CAN bus error and arbitration lost with detailed bit position
  • Supports Programmable clock output
  • Supports Self reception of own messages
  • Supports Single shot transmission
  • Supports message acceptance using single filter and double filter
  • Supports TEC/REC error counter with read/write access
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Supports cluster wake up and go to sleep command
  • Supports LIN status management
  • Self-synchronization in slave nodes without quartz or ceramic resonators
  • Low cost single-wire implementation
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
    • Single Site license option is provided to companies designing in a single site.
    • Multi Sites license option is provided to companies designing in multiple sites.
    • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
    • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

    SmartDV's CAN Controller IP contains following.

    • The CAN Controller interface is available in Source and netlist products.
    • The Source product is delivered in plain text verilog or VHDL or SystemC source code
    • Integration testbench and tests
    • Scripts for simulation and synthesis with support for common EDA tools
    • Documentation contains User's Guide and Release notes.